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WM2617 Dual 10-Bit Serial DAC with Power Down
Production Data, Rev 1.1, October 2000
FEATURES
* * * * * * Two 10-bit DACs Single supply from 2.7V to 5.5V supply operation DNL 0.1 LSB, INL 0.5 LSB Low power consumption * 3mW typical in slow mode * 8mW typical in fast mode TMS320, (Q)SPI, and Microwire compatible serial interface Programmable settling time 4s or 12s typical
DESCRIPTION
The WM2617 is a dual 10-bit voltage output, resistor string, digital-to-analogue converter. A power-on-reset function ensures repeatable start-up conditions. The device has been designed to interface efficiently to industry standard microprocessors and DSPs, including the TMS320 family. The WM2617 is programmed with a 16-bit serial word. The WM2617 has a simple-to-use single 2.7V to 5.5V supply. The digital inputs feature Schmitt triggers for high noise immunity. The number of clocks from the falling edge of NCS are counted automatically. The device is then updated and disabled from accepting further data inputs. Excellent performance is delivered with a typical DNL of 0.1 LSBs. The settling time of the DAC is programmable to allow the designer to optimise speed versus power dissipation. The device is available in an 8-pin SOIC package ideal for space-critical applications. Commercial temperature (0 to 70C) and industrial temperature (-40 to 85C) variants are supported.
APPLICATIONS
* * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation
ORDERING INFORMATION
DEVICE WM2617CD WM2617ID TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 8-pin SOIC 8-pin SOIC
BLOCK DIAGRAM
VDD (8) REFIN(6) REFERENCE INPUT BUFFER X1 DAC OUTPUT BUFFER
TYPICAL PERFORMANCE
0.25 VDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10K/100pF 0.2 0.15 0.1 DNL - LSB
(4) OUTA
DIN (1) data 16-BIT SHIFT REGISTER AND CONTROL LOGIC
10-BIT DAC A LATCH REFERENCE INPUT BUFFER X1
X2
0.05 0 -0.05 -0.1
SCLK (2)
NCS (3)
DAC OUTPUT BUFFER X2 (7) OUTB
10-BIT DAC B HOLDING LATCH
10-BIT DAC B CONTROL LATCH
-0.15 -0.2
POWER-ON RESET
2-BIT CONTROL LATCH
POWERDOWN/ SPEED CONTROL
-0.25 0 256 512 DIGITAL CODE 767 1023
WM2617
(5) AGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2000 Wolfson Microelectronics Ltd.
WM2617
Production Data
PIN CONFIGURATION
DIN SCLK NCS OUTA 1 2 3 4 8 7 6 5 VDD OUTB REFIN AGND
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 NAME DIN SCLK NCS OUTB AGND REFIN OUTA VDD TYPE Digital input Digital input Digital input Analogue output Supply Analogue input Analogue output Supply Serial data input. Serial clock input. Chip select, active low. DAC B analogue output. Analogue ground. Reference voltage input. DAC A analogue output. Positive power supply. DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltage, VDD to AGND Digital input voltage Reference input voltage Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds WM2617CD WM2617ID -0.3V -0.3V 0C -40C -65C MIN MAX 7V VDD + 0.3V VDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN Load resistance Load capacitance Serial Clock Rate Operating free-air temperature SYMBOL VDD VIH VIL VREF RL CL fSCLK TA WM2637CD WM2637ID 0 -40 2 100 20 70 85 C C VDD = 5V VDD = 5V TEST CONDITIONS MIN 2.7 2 0.8 VDD - 1.5 TYP MAX 5.5 UNIT V V V V k
Note: Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
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Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c. power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH = VDD, VIL = 0V VDD = 5.5V, VREF = 2.048V Slow VDD = 5.5V, VREF = 2.048V Fast See Note 8 No load, all digital inputs 0V or VDD DAC code 32 to 1023, 10%-90% Slow Fast See Note 9 DAC code 32 to 1023 Slow Fast See Note 10 Code 511 to 512 0.6 1.6 0.01 1.0 2.5 mA mA A 2k to 10k load See Note 7 0 0.1 VDD - 0.1 0.3 V % INL DNL ZCE GE DC PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 10 bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1 0.1
3 0.1 0.5 10 10
LSB LSB mV % FSR mV/V ppm/C ppm/C
0.5 12 0.6
Power down supply current Dynamic DAC Specifications Slew rate
0.3 2.4
0.5 3.0
V/s V/s
Settling time
12 4 10
s s nV-s
Glitch energy Reference Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN
10 5 VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 VREF = 0.2VPP + 1.024V dc DAC code 512 Slow Fast -60
M pF dB
0.5 1.0 1 -1 8
MHz MHz A A pF
Digital Inputs High level input current Low level input current Input capacitance IIH IIL CI Input voltage = VDD Input voltage = 0V
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Production Data
Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7Vsupply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates. 10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested.
SERIAL INTERFACE
tSUCSS NCS tWCL SCLK tSUDCLK DIN D15 D14 tHDCLK D13 D12 D11 D0 tWCH tSUCS1 tSUCS2
Figure 1 Timing Diagram Test Conditions: RL = 10k, CL = 100pF. VDD = 5V 10%, VREF = 2.048V and VDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL tSUCSS tSUCS1 tSUCS2 tWCH tWCL tSUDCLK tHDCLK TEST CONDITIONS Setup time NCS low before SCLK low Setup time, falling edge of SCLK to rising edge of NCS, external end of write Setup time, rising edge of SCLK to falling edge of NCS, start of next write cycle Pulse duration, SCLK high Pulse duration, SCLK low Setup time, data ready before SCLK falling edge Hold time, data held valid after SCLK falling edge MIN 5 10 5 25 25 5 5 TYP MAX UNIT ns ns ns ns ns ns ns
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Production Data
TYPICAL PERFORMANCE GRAPHS
3 VDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10K/100pF 2
1
INL - LSB
0
-1
-2
-3 0 256 512 DIGITAL CODE 767 1023
Figure 2 Integral Non-Linearity
0.4 0.4
VDD = 3V, VREF = 1V, Input Code = 0
0.35 0.35
VDD = 5V, VREF = 2V, Input Code = 0
0.3
0.3
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
0.25
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0 0 1 2 3 4 5 ISINK- mA 6 7 8 9
Slow
0 10
Fast
0
1
2
3
4
5 ISINK - mA
6
7
8
9
Slow
10
Fast
Figure 3 Sink Current VDD = 3V
2.06
Figure 4 Sink Current VDD = 5V
4.1
VDD = 3V, VREF = 1V, Input Code = 4095
2.055
VDD = 5V, VREF = 2V, Input Code = 4095
4.095
2.05
4.09
2.045
OUTPUT VOLTAGE - V
0 1 2 3 4 5 6 7 8 9 10
Slow
OUTPUT VOLTAGE - V
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025
4.065
2.02 11
Fast ISOURCE- mA
4.06 0 1 2 3 4 5 6 7 8 9 10
Slow
11
Fast
ISOURCE - mA
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
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Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) INPUT 11 1111 : 0000 0000 1111 : 0000 0000 1111
code 1024
OUTPUT
2(VREF ) 1023 1024 513 1024
: 0001 0000 1111
2(VREF ) 2(VREF )
10 10 01
512 = VREF 1024 511 1024 1 1024
2(VREF )
: 0001 0000
2(VREF )
00 00
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN input resistance is 10M and the REFIN input capacitance is typically 5pF. The reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register (see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1 = 20MHz tWCH min+ tWCL min The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 10 bits limits the update rate for large input step transitions.
fSCLKmax =
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 10-bit data word. D15-D12 hold the programmable options which are summarized in Table 3. D15 D14 D13 D12 D11 D10 Program Bits Table 2 Register Map D9 D8 D7 D6 D5 D4 New DAC value (10 bits) D3 D2 D1 x D0 x
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Production Data
PROGRAM BITS D15 1 0 0 X X X X D14 X X X 0 1 X X D13 X X X X X 0 1 D12 X 0 1 X X X X
DEVICE FUNCTION Write to latch A with serial interface register data and latch B updated with buffer latch data. Write to latch B and double buffer latch. Write to double buffer latch only. 12s settling time. 4s settling time. Powered-up operation. Power down mode.
Table 3 Program Bits D15 to D12 Function
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 12s or 4s, typical to within 0.5LSB of final value. This is controlled by the value of D14. A ONE defines a settling time of 4s, a ZERO defines a settling time of 12s.
PROGRAMMABLE POWER DOWN
The power down function is controlled by D13. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts back to the DAC code set prior to power down.
FUNCTION OF THE LATCH CONTROL BITS (D15 AND D12)
PURPOSE AND USE OF THE DOUBLE BUFFER Normally only one DAC output can change after a write. The double buffer allows both DAC outputs to change after a single write. This is achieved by the two following steps. 1. A double buffer only write is executed to store the new DAC B data without changing the DAC A and B outputs. 2. Following the previous step, a write to latch A is executed. This writes the serial interface register (SIR) data to latch A and also writes the double buffer contents to latch B. Thus both DACs receive their new data at the same time and so both DAC outputs begin to change at the same time. Unless a double buffer only write is issued, the latch B and double buffer contents are identical. Thus, following a write to latch A or B with another write to latch A does not change the latch B contents. Three data transfer options are possible. All transfers occur immediately after NCS goes high (or on the sixteenth positive SCLK edge, whichever is earlier) and are described in the following sections. LATCH A WRITE, LATCH B UPDATE (D15 = HIGH, D12 = X) The serial interface register (SIR) data are written to latch A and the double buffer latch contents are written to latch B. The double buffer contents are unaffected. This program bit condition allows simultaneous output updates of both DACs.
SERIAL INTERFACE REGISTER D12 = X D15 = HIGH DOUBLE BUFFER LATCH
LATCH A
TO DAC A
LATCH B
TO DAC B
Figure 7 Latch A Write, Latch B Update LATCH B AND DOUBLE BUFFER WRITE (D15 = LOW, D12 = LOW) The SIR data are written to both latch B and the double buffer. Latch A is unaffected. WOLFSON MICROELECTRONICS LTD PD Rev 1.1 October 2000 7
WM2617
Production Data
SERIAL INTERFACE REGISTER D12 = LOW D15 = LOW DOUBLE BUFFER LATCH
LATCH A
TO DAC A
LATCH B
TO DAC B
Figure 8 Latch B and Double Buffer Write DOUBLE BUFFER ONLY WRITE (D15 = LOW, D12 = HIGH) The SIR data are written to the double buffer only. Latch A and B contents are unaffected.
SERIAL INTERFACE REGISTER D12 = HIGH D15 = LOW DOUBLE BUFFER
LATCH A
TO DAC A
LATCH B
TO DAC B
Figure 9 Double Buffer Only Write OPERATIONAL EXAMPLES 1. changing the latch A data from zero to full code Assuming that latch A starts at zero code (e.g., after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right) 1X0X 1111 1111 11xx to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The other X can be zero or one (don't care). The latch B contents and DAC B output are not changed by this write unless the double buffer contents are different from the latch B contents. This can only be true if the last write was a double buffer-only write. 2. changing the latch B data from zero to full code Assuming that latch B starts at zero code (e.g., after power up), the latch can be filled with 1s by writing (bit D15 on the left, D0 on the right). 0X00 1111 1111 11xx to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The data (bits D0 to D11) are written to both the double buffer and latch B. The latch A contents and the DAC A output are not changed by this write. 3. double buffered change of both DAC outputs Assuming that DACs A and B start at zero code (e.g., after power up), if DAC A is to be driven to mid-scale and DAC B to full-scale, and if the outputs are to begin rising at the same time, this can be achieved as follows:
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First, 0d01 1111 1111 11xx
Production Data
is written (bit D15 on the left, D0 on the right) to the serial interface. This loads the full-scale code into the double buffer but does not change the latch B contents and the DAC B output voltage. The latch A contents and the DAC A output are also unaffected by this write operation. Changing from fast to slow to fast mode changes the supply current which can glitch the outputs, and so D14 (designated by d in the above data word) should be set to maintain the speed mode set by the previous write. Next, 1d0X 1000 0000 00xx is written (bit D15 on the left, D0 on the right) to the serial interface. Bit D14 can be zero to select slow mode or one to select fast mode. The X in bit D12 can be zero or one (don't care). This writes the mid-scale code (100000000000) to latch A and also copies the full-scale code from the double buffer to latch B. Both DAC outputs thus begin to rise after the second write.
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Production Data
PACKAGE DIMENSIONS
D: 8 PIN SOIC 3.9mm Wide Body DM009.B
e
B
8
5
E
H
1
4
L
D h x 45o
A
A1 -C-
C
0.10 (0.004)
SEATING PLANE
Symbols A A1 B C D e E h H L REF:
Dimensions (mm) MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 1.27 BSC 3.80 4.00 0.25 0.50 5.80 6.20 0.40 1.27 o o 0 8
Dimensions (Inches) MIN MAX 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.050 BSC 0.1497 0.1574 0.0099 0.0196 0.2284 0.2440 0.0160 0.0500 o o 0 8
JEDEC.95, MS-012
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-012, VARIATION = AA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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